Conventional techniques for packaging large numbers of integrated circuits (ICs) make use of individual circuit boards. However, as the number of ICs mounted on a single board becomes very large, it becomes difficult to fit all of the necessary interconnections on the board. Moreover, as circuit boards are made larger in order to accommodate increasing numbers of ICs, signal propagation delays are added. In many cases, for example in the design of computers, such additional delay is undesirable, because it reduces processing speed, whereas the very reason for interconnecting very large numbers of components is to create the capacity to process information at a high rate.
As a result of these considerations, designers of electronic devices, for example, of computers, are introducing techniques of three dimensional (3D) packaging. In 3D packaging, rather than mounting the large numbers of ICs on individual circuit boards, designers mount them on multiplicities of circuit boards (or other base members) that are arranged in relatively closely spaced stacks. In a conventional circuit board, all of the electrical interconnections extend along a single plane. A 3D package, by contrast, incorporates not only conventional planar interconnections within single circuit boards, but also interconnections, here called "vertical interconnections," between different boards. In addition, many schemes for 3D packaging include a special circuit board, here called an I/O board. All signals entering or leaving the 3D package pass through the I/O board. Thus, the I/O board incorporates the input and output connections for the 3D package as a whole. The I/O board may be connected to any or all of the other individual circuit boards.
As a result of 3D packaging, some propagation delays are reduced by providing shorter electrical connections and reducing parasitic capacitance along the propagation path. In addition, electrical interconnections are simplified by providing an additional direction, namely the vertical direction, for interconnection. Furthermore, by dividing the total IC-bearing area among a multiplicity of individual circuit boards, 3D packaging can increase the average circuit-board edge length per IC, thus providing more room at the edges of the circuit boards for mounting electrical terminals for interconnections.
These benefits of 3D packaging have made it possible to design packages having a very high volume density of ICs, for example, computing devices having more than 600 VLSI ICs packed in a volume of only about 140 cubic centimeters. Such compact packaging is desirable, for example, for making desktop computers having the power of mainframe computers, or for making computing devices to be installed on aircraft or satellites. However, at such high densities, the removal of heat becomes a significant problem. Hundreds of watts of thermal power may need to be removed from relatively compact packages having a maximum lateral extent of, for example, less than about 10 cm.
Various techniques of heat removal have been applied to 3D packages. For example, various closed-cycle refrigeration systems have been proposed. These include cooling of the 3D package by immersion in a refrigerated coolant, or cooling by thermally contacting the circuit boards with cold plates internally cooled by circulating, refrigerated coolant. Such refrigerated cooling systems are disadvantageous in applications where extreme economy of space is required, because the volume occupied by the refrigeration apparatus makes a significant contribution to the total volume of the package.
Other approaches have used channels, such as tubes or heat pipes, for circulating coolant fluid between a region of a circuit board that is populated with ICs and a heat exchanger. Such a heat exchanger may comprise, for example, fins that are open to the atmosphere, or it may be cooled by a closed-cycle refrigeration system. The use of such circulation channels may be disadvantageous because it is a relatively expensive approach, and heat exchangers may make an undesirable contribution to the total volume of the electronic package.
Still other approaches have relied upon the thermal conduction of heat through a plate or heat sink to a radiative or heat-exchanging structure in contact with the atomosphere. For example, U.S. Pat. No. 4,027,206, issued to Lawrence Y. Lee on May 31, 1977, describes a highly thermally conductive heat sink to which solid state electronic components are secured, and upon which radiator fins are mounted. A circuit board, carrying circuitry, may be mounted directly on the heat sink. The radiator fins are cooled by forced air flowing substantially parallel to the plane of the circuit board or heat sink. A multiplicity of assemblies of circuit boards and heat sinks may be mounted within an enclosure, and the associated radiator fins may be cooled by airflow within the enclosure.
Similarly, U.S. Pat. No. 4,502,098, issued to David F. Brown and Michael J. Anstey on Feb. 25, 1985, describes a circuit assembly in which a multiplicity of plates, carrying integrated circuits, are supported in a stack within a mounting structure having walls. The structure is cooled by directing air through perforations in the walls, such that the air flows over and between the circuit-bearing plates in a direction substantially parallel to the plates. Alternatively, fins can be mounted on the external surfaces of the walls. In that case, heat is conducted, via the plates and the walls, to the fins, which are convectively cooled.
Also similarly, U.S. Pat. No. 4,536,824, issued to Howard W. Barrett and Paul F. Fledderjohann on Aug. 20, 1985, describes a 3D package incorporating cooling channels mounted between ICs and a printed circuit board. The channels are either metal tubes underlying the ICs, or bores in a metal plate that lies under or adjacent the ICs. The package is cooled by forced air flowing through the channels in a direction substantially parallel to the printed circuit boards.
The above-described air-cooled packaging techniques offer certain disadvantages where cooling of very compactly packaged ICs must be achieved while making extremely efficient use of space. Fins are wasteful of space and add possibly undesirable extra weight. Coolant channels are relatively expensive, add weight, and limit the vertical stacking density of circuit boards. More generally, whenever cooling air is directed parallel to the circuit boards, resistance to the flow of air is offered by cool surfaces and by relatively thermally non-conductive surfaces as well as by warm, thermally conductive surfaces, thus reducing the efficiency of the cooling process. This problem can become even more severe as the vertical packing density of circuit boards is reduced, because the resulting constriction of the spaces between successive circuit boards can increase the resistance to flow of the coolant air.